Large area CMOS image sensors that are larger than a standard reticle size can be fabricated by stitching together multiple sensor devices.
FIG. 1 shows a “floor plan” of such a stitched image sensor with blocks B, D, E, F and H stamped multiple times to construct the final chip. FIG. 2 shows more detail the individual repeat blocks. The stamped segments using the same repeat block are physically identical to each other. In essence, this forms multiple different chip parts on the same semiconductor substrate. In this example, the portion A is a timing part, B is a bottom column parallel readout, C is I/O and bias, D is a row driver, E is a pixel array block, F is an I/O device, G is pixel and row timing, and H is a top readout block.
By repeating these parts on the chip, a larger size image can be obtained. However, the operation of the chip foundry often requires that all the stamped parts be identical.
In a column parallel readout image sensor, typically there are identical column readout channels that read out the signal of each pixel. FIG. 3 shows a typical block diagram of the architecture. The data is read from a pixel such as 300, through a programmable gain array amplifier 302, A/D converted at 304, and stored into an SRAM column 310. Once the data is stored into each SRAM column 310, the digital readout block 320 serially reads out each column into a high-speed output port 330. Typically there is a mapping of X number of SRAM columns into 1 Output Port.